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advance information copyright ?2000 alliance semiconductor. all rights reserved. ? as4lc8m8s0 as4lc4m16s0 7/5/00 alliance semiconductor 1 3.3v 4mx16 and 8mx8 cmos synchronous dram features ? pc100/133 compliant ? organization - 2,097,152 words 8 bits 4 banks (8m8) - 1,048,576 words 16 bits 4 banks (4m16) ? fully synchronous - all signals referenced to po sitive edge of clock ? four internal banks controlled by ba0/ba1 (bank select) ?high speed - 133/125/100 mhz - 5.4 ns (133 mhz)/6 ns (125/100 mhz) clock access time ? low power consumption - standby: 7.2 mw max, cmos i/o ? 4096 refresh cycles, 64 ms refresh interval ? auto refresh and self refresh ? automatic and direct precharge ? burst read, single write operation ? can assert random column address in every cycle ? lvttl compatible i/o ? 3.3v power supply ? jedec standard package, pinout and function - 400 mil, 54-pin tsop ii ? read/write data masking ? programmable burst length (1/2/4/8/full page) ? programmable burst sequence (sequential/interleaved) ? programmable cas latency (2/3) pin arrangement a3 v cc a4 v ss v cc dq0 v ccq dq1 dq2 v ssq dq3 dq4 v ccq dq5 dq6 v ssq dq7 v cc ldqm v ss dq15 v ssq dq14 dq13 v ccq dq12 dq11 v ssq dq10 dq9 v ccq dq8 v ss nc udqm clk cke 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 54-pin tsop 23 24 25 32 31 30 we cas ras cs ba0 ba1 a10 a0 a1 a2 nc a11 a9 a8 a7 a6 a5 26 27 29 28 nc dq1 nc dq2 nc dq3 nc nc dq7 nc dq6 nc dq5 nc dq4 nc dqm 4lc4m16s0 a3 v cc v cc dq0 v ccq v ssq v ccq v ssq v cc we cas ras cs ba0 ba1 a10 a0 a1 a2 a4 v ss v ss v ssq v ccq v ssq v ccq v ss nc clk cke nc a11 a9 a8 a7 a6 a5 as4lc4m16s0 as4lc4m16s0 pin designation pin(s) description dqm (8m8) udqm/ldqm (4m16) output disable/write mask a0 to a11 address inputs ba0, ba1 bank select inputs dq0 to dq7 (8m8) dq0 to dq15 (4m16) input/output ras row address strobe cas column address strobe we write enable cs chip select v cc , v ccq power (3.3v 0.3v) v ss , v ssq ground clk clock input cke clock enable selection guide symbol -75 (pc133) -8 -10f (pc100) -10 (pc100) unit bus frequency f max 133 125 100 100 mhz minimum clock access time cl = 2 t ac CC6Cns cl = 3 t ac 5.4 6 C 6 ns minimum setup time t s 1.5 2 2 2 ns minimum hold time t h 0.81.01.01.0ns minimum ras to cas delay t rcd 3323cycles minimum ras precharge time t rp 3323cycles remarks: (cl/t rcd /t rp ) 3/3/3 3/3/3 2/2/2 3/3/3
? 2 alliance semiconductor 7/5/00 as4lc4m16s0 as4lc16m4s0 functional description the as4lc8m8s0 and as4lc4m16s0 are high-performance 64-megabit cmos synchronous dynamic random access memory (sdram) devices organized as 2,097,152 words 8 bits 4 banks, and 1,048,576 words 16 bits 4 banks, respectively. very high bandwidth is achieved using a pipelined architecture where all inputs and outputs are referenced to the rising edge of a common clock. programmable burst mode can be used to read up to a full page of data without selecting a new column address. the four internal banks can be alternately accessed (read or write) at the maximum clock frequency for seamless interleaving operations. this provides a significant advantage over asynchronous edo and fast page mode devices. this sdram product also features a programmable mode register, allowing users to select read latency as well as burst length and type (sequential or interleaved). lower latency improves first data access in terms of clk cycles, while higher latency improves maximum frequency of operation. this feature enables flexible performance optimization for a variety of applications. dram commands and functions are decoded from control inputs. basic commands are as follows: the 64 mb dram devices are available in 400-mil plastic tsop ii packages and have 54 pins in each configuration. both devices operate with a power supply of 3.3v 0.3v. multiple power and ground pins are provided for low switching noise and emi. inputs and outputs are lvttl-compatible. logic block diagram ? for as4lc8m8s0, banks a-d will read 8m8 (40965128). ? for as4lc4m16s0, dqm will be udqm and ldqm. ? mode register set ? deactivate bank ? deactivate all banks ? select row; activate bank ? select column; write ? select column; read ? deselect; power down ? cbr refresh ? auto precharge with read/write ? self-refresh ras cas we clk cke clock generator mode register command decoder control logic row address buffer refresh counter column address buffer burst counter row decoder column decoder and latch circuit data control circuit latch circuit input and output buffer dq a[11:0] dqm ? cs bank select ba0, ba1 bank a ? 1m16 (409625616) bank b ? 1m16 (409625616) bank c ? 1m16 (409625616) bank d ? 1m16 (409625616) sense amplifier
? as4lc8m8s0 as4lc4m16s0 7/5/00 alliance semiconductor 3 pin descriptions pin name description clk system clock all operations synchronized to rising edge of clk. it also inc rements the burst counters. cke clock enable controls clk input. if cke is high, the next clk rising edge is valid. if cke is low, the internal clock is suspended from the next clock cycle and the burst address and output states are frozen. pulling cke low has the following effects: all banks idle: precharge power down and self refresh. row active in any bank: active power down. burst/access in progress: clock suspend. when in power down or self refresh mode, cke becomes asynchronous until exiting the mode. cs chip select enables or disables device operation by masking or enabling all inputs except clk, cke, udqm/ldqm ( 16), dqm ( 8). a0~a11 address row and column addresses are multiplexed. row address: a0~a11. column address (8m 8): a0~a8. column address (4m 16): a0~a7. ba0, ba1 bank select memory cell array is organized in 4 banks. ba0 and ba1 select which internal bank will be active during activate, read, write, and precharge operations. ras row address strobe enables row access and precharge operation. when ras is low, row address is latched at the rising edge of clk. cas column address strobe enables column access. when cas is low, starting column address for the burst access operation is latched at the rising edge of the clk. we write enable enables write operation and row precharge operation. 8: dqm 16: udqm/ldqm output disable/ write mask controls i/o buffers. when dqm is high, output buffers are disabled during a read operation and input data is masked during a write operation. dqm latency is 2 clocks for read and 0 clocks for write. for 16, ldqm controls lower byte (dq0C7) and udqm controls upper byte (dq8C15). for 8, only one dqm controls the 8 dqs. udqm and ldqm are considered same state when referenced as dqm. dq0~dq15 data input/output data inputs/outputs are multiplexed. data bus for 8m 8 is dq0~dq7 only. v dd /v ss power supply/ground power and ground for core logic and input buffers. v ddq /v ssq data output power/ ground power and ground for data output buffers.
? 4 alliance semiconductor 7/5/00 as4lc4m16s0 as4lc16m4s0 commands 1 op = operation code. a0~a11 and ba0~ba1 program keys. 2 mrs can be issued only when all banks are precharged. a new command can be issued 1 clock cycle after mrs. 3 auto refresh functions similarly to cbr dram refresh. however, precharge is automatic. auto/self refresh can only be issued after all banks are precharged. 4 ba0~ba1: bank select addresses. if a10/ap is high at row precharge, ba0 and ba1 are ignored and all banks are selected. during read, write, row active, and prechage: if ba0 and ba1 are low, bank a is selected. if ba0 = low and ba1 = high, bank b is selected. if ba0 = high and ba1 = low, bank c is selected. if ba0 and ba1 are high, bank d is selected. 5 a new read/write command to the same bank cannot be issued during a burst read/write with auto precharge. a new row active command can be issued after t(t rp /t ck + bl +) cycles. 6 burst stop command valid at every burst length. 7 dqm sampled at positive edge of clk. data-in may be masked at every clk (write dqm latency is 0). data-out mask is active 2 clk cycles after issuance. (read dqm latency is 2). command cke n-1 cke n cs ras cas we dqm ba0/ ba1 a10 a9Ca0 dq note register mode register set h * *v:valid;x:don?tcare;h:logichigh;l:logiclow. hll l l x op code x1,2 refresh auto refresh h h l l l h x C x C x 3 self refresh entry h l l l l h x C C 3 exit l h lhhh x C C 3 hxxx x C C 3 bank activate h h l l h h x v row address x read auto precharge disable hhlhlhxv l column address x 4 auto precharge enable h 4,5 write auto precharge disable hhlhllxv l column address valid 4 auto precharge enable h 4,5 burst stop h h l h h l x x active 6 precharge selected bank hhllhlx vl xx4 all banks x h clock suspend or active power down entry h l hxxx xxx x x lvvv exit l hxxxx precharge power down mode entry h l hxxx xxx x x lhhh exit l h hxxx lvvv dqm write enable/output enable hh xxxx h xx x x7 write inhibit/output high-z no operation command h x hxxx x xx x x lhhh x
? as4lc8m8s0 as4lc4m16s0 7/5/00 alliance semiconductor 5 mode register fields ? rfu = 0 during mrs cycle. register programmed with mrs address a11~a10a9a8a7a6a5a4a3a2a1a0 function rfu ? wbl tm cas latency bt burst length write burst length burst type a9 length a3 ty pe 0 programmed burst length 0sequential 1 interleaved 1single burst test mode a8 a7 type 0 0 mode register set 01 reserved 10 reserved 1 1 reserved cas latency burst length a6 a5 a4 latency a2 a1 a0 bt = 0 bt = 1 0 0 0 reserved 0 0 0 1 1 0 0 1 reserved 0 0 1 2 2 01 0 2 0 1 0 4 4 01 1 3 0 1 1 8 8 1 x x reserved 1 0 0 reserved reserved 1 0 1 reserved reserved 1 1 0 reserved reserved 1 1 1 full page reserved
? 6 alliance semiconductor 7/5/00 as4lc4m16s0 as4lc16m4s0 recommended operating conditions ? v il min = C1.5v for pulse widths less than 5 ns. ? i oh = C2ma, and i ol = 2ma. recommended operating conditions apply throughout this document unless otherwise specified. absolute maximum ratings note: stresses greater than those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions outside those indicated in the operational sections of this specificat i on is not implied. exposure to absolute maximum rating conditions for extended periods may affect reliability. capacitance notes 1 this parameter is sampled. v cc = v ccq = 3.3v; f = 1mhz; t a = 23 c; pin under test biased at 1.4v. 2 max value is specified for C10, C10f, and C8. 3 for C75 part, max = 3.5 pf. 4 for C75 part, max = 3.8 pf. 5 for C75 part, max = 6.0 pf. parameter symbol min max unit supply voltage v cc ,v ccq 3.0 3.6 v gnd 0.0 0.0 v input voltage v ih 2.0 v cc + 0.3 v v il C0.3 ? 0.8 v output voltage ? v oh 2.4 C v v ol C0.4v input leakage current any input 0v v in v cc i l C5 +5 ua output leakage current dqs are disabled 0v v out v ccq i oz C5 +5 ua ambient operating temperature t a 070c parameter symbol min max unit input voltage v in ,v out C1.0 +4.6 v power supply voltage v cc ,v ccq C1.0 +4.6 v storage temperature (plastic) t stg C55 +150 c power dissipation p d C1w short circuit output current i out C50ma parameter symbol min max unit notes input capacitance: clk c i1 2.5 4 pf 1, 2, 3 input capacitance: all other input-only pins c i2 2.5 5 pf 1, 2, 4 input/output capacitance c i/o 4.0 6.5 pf 1, 2, 5
? as4lc8m8s0 as4lc4m16s0 7/5/00 alliance semiconductor 7 i dd specifications and conditions 1,2,3 (0 c t a 70 c, v dd , v ddq = +3.3v 0.3v) notes 1i dd specifications are tested after proper initialization of the device. 2i dd is dependent on output loading and clock cycle time. values are specified with minimum cycle time and outputs open. 3i dd tests have v il = 0v and v ih = 3v. 4i dd current will decrease at lower cas latencies. this is because the lower the latency, the lower the clock cycle time. 5 address transitions average one transition every two clock cycles. parameter symbol max units notes C75 C8 C10f/10 operating current: active mode; burst = 2; read or write; t rc = t rc (min); cas latency = 3 i dd1 115 95 95 ma 4, 5 standby current: power-down mode; all banks idle; cke = low i dd2 222ma4,5 standby current: active mode; cke = high; cs# = high; all banks active after t rcd met; no accesses in progress i dd3 45 35 35 ma 4, 5 operating current: burst mode; continuous burst; read or write; all banks active; cas latency = 3 i dd4 140 130 120 ma 4,5 auto refresh current: cke = high; cs# = high t rfc = t rfc (min); cl = 3 i dd5 210 210 190 ma 4, 5 t rfc = 15.625ms; cl = 3 i dd6 50 50 40 ma 4,5 self-refresh current: cke 0.2v i dd7 111ma4,5
? 8 alliance semiconductor 7/5/00 as4lc4m16s0 as4lc16m4s0 ac parameters common to all waveforms sym parameter cas latency -75 -8 -10f -10 unit notes min max min max min max min max t rrd row active to row active delay 15 C 20 C 20 C 20 C ns 1 t rcd ras to cas delay time 20 C 20 C 20 C 30 C ns 1 t rp row precharge 20 C 20 C 20 C 30 C ns 1 t ras row active 44 C 50 C 50 C 60 C ns 1 trc row cycle time 66 C 70 C 70 C 90 C ns 1 t cdl last data in to new column address delay 1C1C1C1Cclk2 t rdl last data in to row precharge 2 C 2 C 2 C 2 C clk 2 t bdl last data in to burst stop 1 C 1 C 1 C 1 C clk 2 t ccd column address to column address delay 1C1C1C1Cclk3 t ck clk cycle time 37.5C8 C 10 C 10 C ns 4 210C10 C 15 C 15 C 4 t ac clk to valid output delay @ 50pf 35.4C6 C 6 C 6 C ns 4,5,7 26C6C 6 C 6 C 4,5,7 t oh output data hold time @ 50 pf 32.7C3 C 3 C 3 C ns 4,5,7 23C3C 3 C 3 C 4,5,7 t ch clk high pulse width 2.5 C 3 C 3 C 3 C ns 6 t cl clk low pulse width 2.5 C 3 C 3 C 3 C ns 6 t as add setup time 1.5 C 2 C 2 C 2 C ns 6 t ah add hold time 0.8 C 1 C 1 C 1 C ns 6 t slz clk to output in low z 1 C 1 C 1 C 1 C ns 5 t shz clk to output in high z 3C6C 7 C 7 C 7 ns 2C6C 7 C 7 C 7 t ckh cke hold time 0.8C1C1C1Cns t cks cke setup time 1.5 C 2 C 2 C 2 C ns t cmh cs , ras , cas , we , dqm hold time 0.8C1C1C1Cns t cms cs , ras , cas , we , dqm setup time 1.5C2C2C2Cns t dh data in hold time 0.8 C 1 C 1 C 1 C ns t ds data in setup time 1.5 C 2 C 2 C 2 C ns
? as4lc8m8s0 as4lc4m16s0 7/5/00 alliance semiconductor 9 ac parameters common to all waveforms (continued) notes 1 minimum clock cycles = (minimum time / clock cycle time) rounded up. 2 minimum delay required to complete write. 3 column address change allowed every cycle. 4 parameters dependent on cas latency. 5if clock rising time > 1ns, (tr/2-0.5)ns should be added to parameter. 6 if (tr and tf) > 1ns, [(tr+tf)/2-1]ns should be added to parameter. 7 outputs measured at 1.5v with 50pf load only without resistive termination. burst sequence (bl = 4) burst sequence (bl = 8) sym parameter cas latency -75 -8 -10 f -10 unit notes min max min max min max min max t dqd dqm to input data delay 1 C 1 C 1 C 1 C clk t dqm dqm to data mast during writes 0 C 0 C 0 C 0 C clk t dqz dqm to data high z during reads 2C2C2C2Cclk t dw d write command to input data delay 0C0C0C0Cclk t dal data-in to active command 5 C 5 C 5 C 5 C clk t mrd load mode register to active/ refresh command 1C1C1C1Cclk t roh data-out high z from precharge/burst stop command 33C3 C 3 C 3 Cclk4 22C2 C 2 C 2 Cclk4 t cked cke to clock disable or power- down entry mode 1C1C1C1Cclk t ped cke to clock enable or power- down exit mode 1C1C1C1Cclk initial address sequential interleave a1 a0 0 0 01230123 0 1 12301032 1 0 23012301 1 1 30123210 initial address sequential interleave a2 a1 a0 0 0 0 0123456701234567 0 0 1 1234567010325476 0 1 0 2345670123016745 0 1 1 3456701232107654 1 0 0 4567012345670123 1 0 1 5670123454761032 1 1 0 6701234567452301 1 1 1 7012345676543210
? 10 alliance semiconductor 7/5/00 as4lc4m16s0 as4lc16m4s0 device operation command pin settings description power up the following sequence must be performed prior to normal operation. 1. apply power, start clock, and assert cke and dqm high. all other signals are nop. 2. after power-up, pause for a minimum of 200s. cke/dqm = high; all others nop. 3. precharge both banks. 4. perform mode register set command to initialize mode register. 5. perform a minimum of 8 auto refresh cycles to stabilize internal circuitry. (steps 4 and 5 may be interchanged.) mode register set cs = ras = cas = we = low; a0~a11 = opcode the mode register stores the user selected opcode for the sdram operating modes. the cas latency, burst length, burst type, test mode and other vendor specific functions are selected/programmed during the mode register set command cycle. the default setting of the mode register is not defined after power-up. the power-up and mode register set cycle must be executed prior to normal sdram operation. refer to the mode register set table and timing for details. device deselect and no operation cs = high the sdram performs a no operation (nop) when ras , cas , and we = high. since the nop performs no operation, it may be used as a wait state in performing normal sdram functions. the sdram is deselected when cs is high. cs high disables the command decoder such that ras , cas , we and address inputs are ignored. device deselection is also considered a nop. bank activation cs = ras = low; cas = we = high; a0~a10 = row address; ba0~ba1 = bank select the sdram is configured with four internal banks. use the bank activate command to select a row in one of the idle banks. initiate a read or write operation after t rcd (min) from the time of bank activation. burst read cs = cas = a10 = low; ras = we = high; ba0~ba1 = bank select, a0~a8 = column address; (a9 = dont care for 8m 8; a8,a9 = dont care for 4m 16) use the burst read command to access a consecutive burst of data from an active row in an active bank. burst read can be initiated on any column address of an active row. the burst length, sequence and latency are determined by the mode register setting. the first output data appears after the cas latency from the read command. the output goes into a high impedance state at the end of the burst (bl = 1,2,4,8) unless a new burst read is initiated to form a gapless output data stream. terminate the burst with a burst stop command, precharge command to the same bank or another burst read/write. burst write cs = cas = we = a10 = low; ras = high; a0~a9 = column address; (a9 = dont care for 8m 8; a8,a9 = dont care for 4m 16) use the burst write command to write data into the sdram on consecutive clock cycles to adjacent column addresses. the burst length and addressing mode is determined by the mode register opcode. input the initial write address in the same clock cycle as the burst write command. terminate the burst with a burst stop command, precharge command to the same bank or another burst read/write. udqm/ldqm ( 16), dqm ( 8) operation use dqm to mask input and output data on a cycle-by-cycle basis. it disables the output buffers in a read operation and masks input data in a write operation. the output data is invalid 2 clocks after dqm assertion (2 clock latency). input data is masked on the same clock as dqm assertion (0 clock latency).
? as4lc8m8s0 as4lc4m16s0 7/5/00 alliance semiconductor 11 device operation (continued) command pin settings description burst stop cs = we = low; ras = cas = high use burst stop to terminate burst operation. this command may be used to terminate all legal burst lengths. bank precharge cs = a10 = ras = we = low; cas = high; a11 = bank select; a0~a9 = dont care the bank precharge command precharges the bank specified by ba0 and ba1. the precharged bank is switched from active to idle state and is ready to be activated again. assert the pr echarge command after t ras (min) of the bank activate command in the specified bank. the precharge operation requires a time of t rp (min) to complete. precharge all cs = ras = we = low; cas = a10 = high; ba0~ba1 = bank select; a0~a9 = dont care the precharge all command precharges all four banks simultaneously. all four banks are switched to the idle state on precharge completion. auto precharge cs = cas = we (write) = low; ras = we (read) = a10 = high; ba0~ba1 = bank select; a0~a9 = column address; (a9 = dont care for 2m 8; a8,a9 = dont care for 1m 16) during auto precharge, the sdram adjusts internal timing to satisfy t ras (min) and t rp for the programmed cas latency and burst length. couple the auto precharge with a burst read/write operation by asserting a10 to a high state at the same time the burst read/write commands are issued. at auto precharge completion, the specified bank is switched from active to idle state. note that no new commands to the bank can be issued until the specified bank achieves the idle state. auto precharge doesnt work with full-page burst. clock suspend/power down mode entry cke = low when cke is low, the internal clock is frozen or suspended from the next clock cycle and the state of the output and burst address are frozen. if all banks are idle and cke goes low, the sdram enters power down mode at the next clock cycle. when in power down mode, no input commands are acknowledged as long as cke remains low. to exit power down mode, raise cke high before the rising edge of clk. clock suspend/power down mode exit cke = high resume internal clock operation by asserting cke high before the rising edge of clk. subsequent commands can be issued one clock cycle after the end of the exit command. auto refresh cs = ras = cas = low; we = cke = high; a0~a11 = dont care sdram storage cells must be refreshed every 64ms to maintain data integrity. use the auto refresh command to refresh all rows in all banks of the sdram. the row address is provided by an internal counter which increments automatically. auto refresh can only be asserted when all four banks are idle and the device is not in the power down mode. the time required to complete the auto refresh operation is t rc (min). use nops in the interim until the auto refresh operation is complete. this is the most common refresh mode. it is typically performed once every 15.6us or in a burst of 4096 auto refresh cycles every 64ms. all four banks will be in the idle state after this operation. self refresh cs = ras = cas = cke = low; we = high; a0~a11 = dont care self refresh is another mode for refreshing sdram ce lls. in this mode, refresh address and timing are provided internally. self refresh entry is allowed only when all four banks are i dle. the internal clock and all input buffers with the exception of cke are disabled in this mode. exit self refresh by restarting the external clock and then asserting cke high. nops must follow for a time of t rc (min) for the sdram to reach the idle state where normal operation is allowed. if burst auto refresh is used in normal operation, burst 4096 auto refresh cycles immediately after exiting self refresh.
? 12 alliance semiconductor 7/5/00 as4lc4m16s0 as4lc16m4s0 mode register set command waveform mrs can be issued only when both banks are idle. precharge waveforms precharge can be asserted after t ras (min). the selected bank will enter the idle state after t rp .. the earliest assertion of the precharge command without losing any burst data is show below. (normal write; bl = 4) (normal read; bl = 4) auto precharge waveforms a10 controls the selection of auto precharge during the read or write command cycle. (write with auto precharge; bl = 4) (read with auto precharge; bl = 4) * the row active command of the precharge bank can be issued after t rp from this point. at burst read/write with auto precharge, cas interrupt of the same bank is illegal; other bank is described below. clk cmd pre mrs act t rp t rsc (min) clk cmd dq we d 0 d 1 d 2 d 3 pre clk cmd dq(cl2) dq(cl3) read data pre q 0 q 1 q 2 q 3 q 0 q 1 q 2 q 3 clk cmd dq we d 0 d 1 d 2 d 3 auto precharge starts* auto precharge starts* clk cmd dq(cl2) dq(cl3) read data q 0 q 1 q 2 q 3 q 0 q 1 q 2 q 3
? as4lc8m8s0 as4lc4m16s0 7/5/00 alliance semiconductor 13 concurrent auto-p waveforms according to intel?s specification, auto-p burst interruption is allowed by another burst provided that the interrupting burst is in a different bank than the ongoing burst. (a) rd-p interrupted by rd in another bank (cl = 3, bl = 4) (b) rd-p interrupted by wr in another bank (cl = 2, bl = 8) (c) wr-p interrupted by rd in another bank (cl = 2, bl = 4) * the row active command of the precharge bank can be issued after t rp from this point. clk cmd rd-p (a) dq a 0 a 1 b 0 b 1 b 2 b 3 bank a precharge starts * rd (b) clk cmd rd-p (a) dq q a0 q a1 d n(b0) d (b1) d (b2) bank a precharge starts * wr (b) dqm d (b7) clk cmd wrp (a) dq d (a0) d (a1) q b0 q b1 q b2 bank a precharge starts * rd (b) q b3
? 14 alliance semiconductor 7/5/00 as4lc4m16s0 as4lc16m4s0 (d) wr-p interrupted by wr in another bank (cl = 3, bl = 4) * the row active command of the precharged bank can be issued after t rp from this point. clock suspension read waveforms (bl = 8) clk cmd wrp (a) dq d a0 d a1 d a2 d b0 db 1 wr (b) d b2 d b3 bank a precharge starts * clk external clk internal cke dqm dq q 1 q 2 q 3 q 4 q 6 open open clk external clk internal cke dqm dq q 1 q 2 q 3 q 4 q 6 open clk external clk internal cke dqm dq q 1 q 2 q 3 q 4 q 6 q 5
? as4lc8m8s0 as4lc4m16s0 7/5/00 alliance semiconductor 15 clock suspension write waveforms (bl = 8) read/write interrupt timing read interrupted by read (cl = 2, bl = 4) t ccd = cas to cas delay (= 1 clk) clk external clk internal cke dqm dq d 1 d 2 d 3 dqm mask d 5 d 6 cke mask clk external clk internal cke dqm dq dqm mask cke mask d 1 d 2 d 3 d 5 d 6 clk external clk internal cke dqm dq d 1 d 2 d 3 d 4 d 6 d 5 clk cmd add dq (cl2) dq (cl3) read data read data ab qa 0 qb 0 qb 1 qb 2 qb 3 qa 0 qb 0 qb 1 qb 2 qb 3 t ccd
? 16 alliance semiconductor 7/5/00 as4lc4m16s0 as4lc16m4s0 write interrupted by write (bl = 4) t ccd = cas to cas delay (= 1 clk) t cdl = last address in to new column addres delay (= 1 clk) write interrupted by read (cl = 2, bl = 4) t ccd = cas to cas delay (= 1 clk) t cdl = last address in to new column addres delay (= 1 clk) read interrupted by write (cl = 3, bl = 4) * to prevent bus contention, maintain a gap between data in and data out. burst termination burst operations may be terminated with a read, write, burst stop, or precharge command. when burst stop is asserted during the read cycle, burst read data is terminated and the data bus goes to high z after cas latency. when burst stop is asserted during the write cycle, burst write data is terminated and the databus goes to high z simultaneously. burst stop command waveform, read cycle (bl = 8) clk cmd add dq da 0 db 0 db 1 db 2 db 3 a 0 b 0 write data write data t ccd t cdl t cdl clk cmd add dq (cl2) dq (cl3) write data read data ab da 0 qb 0 qb 1 qb 2 qb 3 da 0 qb 0 qb 1 qb 2 qb 3 t ccd clk cmd dqm dq read data write data* d 0 d 1 d 2 d 3 q 0 clk cmd dq (cl = 2) dq (cl = 3) read data burst stop read data q 0 q 1 q 2 q 0 q 1 q 2
? as4lc8m8s0 as4lc4m16s0 7/5/00 alliance semiconductor 17 write cycle precharge command a precharge command can be used to interrupt burst read/write operation during the read cycle. during rd, burst read is terminated and o/p goes to high z after cas latency. the same bank can be activated after t rp . during write, burst write operation is terminated immediately. data written two cycles prior to the precharge command will be correctly stored. set dqm high one cycle before precharge command and hold it high until precharge command to mask and avoid w riting invalid data. read cycle (cl = 2) read cycle (cl = 3) write cycle (bl = 8) clk cmd dq burst stop write data (cl = 2,3) q 0 q 1 q 2 q 3 clk cmd dq read data pre act q 0 q 1 q 2 q 3 t rp clk cmd dq read data pre act q0 q1 q2 q3 clk cmd dq write data pre act d 0 d 1 d 2 q 4 t rp d 3 masked dqm
? 18 alliance semiconductor 7/5/00 as4lc4m16s0 as4lc16m4s0 auto refresh waveform ? if a10 = high, then ba0/ba1 = dont care; if a10 = low, then ba0/ba1 = bank select. self refresh waveform clk cs ras cas we ba0/ba1 a10 ? a0?a9 dqm cke dq t rp t rc t rc auto refresh precharge all banks auto refresh auto refresh banks clk cs ras cas we ba0/ba1 a0?a9,a11 dqm cke dq precharge all banks t rc self refresh entry self refresh exit arbitrary cycle self refresh cycle a10 raa ra a
? as4lc8m8s0 as4lc4m16s0 7/5/00 alliance semiconductor 19 power down mode waveform enter power down mode by pulling cke low. all input/output buffers (except cke buffer are turned off in power down mode. when cke goes high, command input must be equal to no operation at next clk rising edge. read/write waveform (bl = 8, cl = 3) power down mode active standby clk cs ras cas we ba0/ba1 a10 a0?a9,a11 dqm cke dq ra a ra a ca a ca x ra a ra a bank activate power down mode entry power down mode exit nop power down mode entry power down mode precharge standby nop power down mode exit bank activate ab 0 ra a clk cs ras cas we ba0/ba1 a10 a0-a9,a11 dqm cke dq ca a ra a ca b ra b ra b t ras t rp t rp aa 0 aa 5 aa 4 aa 3 aa 2 aa 1 ab 5 ab 4 ab 3 ab 2 ab 1 bank activate read qqqq q q dddd d d bank activate write precharge t rp
? 20 alliance semiconductor 7/5/00 as4lc4m16s0 as4lc16m4s0 burst read/single write waveform (bl = 4, cl = 3) interleaved bank read waveform (bl = 4, cl = 3) ? ba0 and ba1 together determine which bank undergoes operations. single clk cs ras cas we ba0/ba1 a10 a0?a9,a11 dqm cke dq ra a ca a ra a ca b ca r ca d activate read read write a a0 a a5 a a4 a a3 a a2 a a1 a d0 a d3 a d2 a d1 q q q q qq q q d d clk cs ras cas we ba0/ba1 ? a10 a0?a9, a11 dqm cke dq t ccd t ccd t ccd t ras t rp t rcd ra a rb a ca a ca b cb b ca c qa a0 qa a3 qa a2 qa a1 qb a0 qa b1 qa b0 qb a1 qa b2 qa c2 qa c1 qa c0 qb b0 qb b3 qb b2 qb b1 bank a bank b active read read read read precharge ra a cb a precharge rb a bank bank bank bank bank bank bank bank bank t rcd
? as4lc8m8s0 as4lc4m16s0 7/5/00 alliance semiconductor 21 interleaved bank read waveform (bl = 4, cl = 3, autoprecharge) ? ba0 and ba1 together determine which bank undergoes operations. ap = internal precharge begins. interleaved bank read waveform (bl = 8, cl = 3) ? ba0 and ba1 together determine which bank undergoes operations. clk cs ras cas we a10 a0?a9, a11 dqm cke dq t rc t rc t rc t rc t ras t rp t ras t ras t rp t ras t rcd t rcd t rcd t rcd qa a0 qa a3 qa a2 qa a1 qb b3 qb b2 qb b1 qa a0 qa a3 qa a2 qa a1 qb b0 qb b2 qb b1 raa ra a ra b ra b ca a cb b cb d ra d ra d t rrd t rrd t rrd t rrd bank a bank b active read active ap active read ap read active ap read active ba0/ba1 ? bank bank bank bank bank bank bank bank bank t rp t ras ra c ra c cb c ra e ra e qb b0 clk cs ras cas we a10 a0?a9, a11 dqm cke dq t rc t rc t rc t ras t ras t ras t rp t rp t rp t rcd t rcd t rcd ra a ra a ca a rb b rb b cb b ra c ra c ca c qa a0 qa a1 qa a2 qa a3 qa a4 qa a5 qa a6 qb b0 qb b1 qb b4 qb b5 qb b6 qb b7 qa c0 qa c1 bank a bank b active read precharge read precharge active precharge active read ba0/ba1 ? bank bank bank bank bank bank bank bank bank
? 22 alliance semiconductor 7/5/00 as4lc4m16s0 as4lc16m4s0 interleaved bank read waveform (bl = 8, cl = 3, autoprecharge) ? ba0 and ba1 together determine which bank undergoes operations. ap = internal precharge begins. interleaved bank write waveform (bl = 8) ? ba0 and ba1 together determine which bank undergoes operations. clk cs ras cas we a10 a0?a9, a11 dqm cke dq qa a0 qa a1 qa a2 qa a3 qa a4 qa a5 qa a6 qb b0 qb b1 qa a7 t rc t rc t ras t ras t rp tras t rp t rcd t rcd t rcd ca a ra a rb b rb b ca b ca c ra a ra c ra c qb b4 qb b5 qb b6 qa c0 qa c0 t rrd t rrd active read active read bank a bank b ap active read ap ba0/ba1 ? bank bank bank bank bank bank clk cs ras cas we a10 a0-a9,a11 dqm cke dq t rc t ras t rp t ras t rcd t rcd t rcd ca a ra a rb b rb b ca b ca c ra a ra c ra c da a0 da a1 da a4 da a5 da a6 da a7 db b0 db b1 db b2 db b3 db b4 db b5 db b6 db b7 da c0 da c1 da c2 active write active write bank a bank b active write precharge precharge ba0/ba1 ? bank bank bank bank bank bank
? as4lc8m8s0 as4lc4m16s0 7/5/00 alliance semiconductor 23 interleaved bank write waveform (bl = 8, autoprecharge) ? ba0 and ba1 together determine which bank undergoes operations. ap = internal precharge begins clk cs ras cas we a10 a0-a9.a11 dqm cke dq active write active write bank a bank b active write ap bank a ap bank b t rc t ras t rp t ras t ras t rcd t rcd t rcd ca a ra a rb b rb b ca b ca c ra a ra c ra c da a0 da a1 da a4 da a5 da a6 da a7 db b0 db b1 db b2 db b3 db b4 db b5 db b6 db b7 da c0 da c1 da c2 ba0/ba1 ? bank bank bank bank bank bank
? 24 alliance semiconductor 7/5/00 as4lc4m16s0 as4lc16m4s0 package dimensions ac test conditions ordering information part numbering system part C75 C8 C10 C10f tsop ii, 400 mil, 54-pin as4lc8m8s0-75tc as4lc8m8s0-8tc as4lc8m8s0-10tc AS4LC8M8S0-10FTC tsop ii, 400 mil, 54-pin as4lc4m16s0-75tc as4lc4m16s0-8tc as4lc4m16s0-10tc as4lc4m16s0-10ftc as4 lc xxxs0 Cxx t c dram prefix lc = 3.3v cmos device number for synchronous dram 1/frequency package (device dependent): tsop ii 400 mil, 54 pin commercial temperature range, 0 c to 70 c 54-pin tsop ii min (mm) max (mm) aC 1.2 a 1 0.05 C a 2 0.95 1.05 b0.30 0.45 c 0.12 0.21 d 22.12 22.32 e 10.03 10.29 e 0.80 (typical) h e 11.56 11.96 l 0.40 0.60 d he 1234567891011121314 54 53 52 51 50 49 48 47 46 45 44 43 42 41 15 16 40 39 17 18 19 20 38 37 36 35 c l a 1 a 2 e 54-pin tsop ii 0C5 21 34 22 23 24 25 33 32 31 30 e a b 26 27 29 28 - input reference levels of vih = 2.0v and vil = 0.8v - output reference levels = 1.4v - input rise and fall times: 2 ns c load = 50 pf d out +1.4v figure a: equivalent output load 50w z0 = 50w

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